The present invention generally relates to data receivers, and more specifically, to coupling systems for data receivers.
Data receivers are formed on integrated circuits for receiving data from outside the integrated circuit. In order to increase adaptability, a data receiver may be designed to receive both AC and DC coupled input signals.
Data receivers require certain DC voltage bias levels to be present at the inputs of the first-stage signal amplifier which connects to an external data transmission line, to permit correct operation of the amplifier. In a typical high data range signaling application, differential transmission lines are used to convey the data information. The average voltage level of the signals on the two differential lines is called the “common mode” voltage. In general, data transmission devices which connect to the data receivers may not provide the required common-mode bias level to enable correct operation of the receiver input device. To solve this problem, common practice in the art is to employ the use of series “DC block” capacitors in the external line to isolate the DC bias level of the receiver input circuitry from the active transmitter elements. The external “DC block” capacitors enable the receiver to set its input common mode voltage independently of the transmission device to enable optimal operation of the receiver system.
A problem with the use of external DC block capacitors is the need for via drops to the data transmission lines (normally realized as impedance controlled differential stripline) to connect the DC block capacitor to the transmission lines in multi-layer boards. These via drops add unwanted impedance discontinuity, which degrades the signal quality. This problem becomes more and more severe at extremely high data rates such as 25 Gb/s, which is close to the state of the art data rate in electrical interconnect signaling systems today. The impedance discontinuity results in both signal level loss and signal time dispersion resulting from characteristic impedance mismatch which generates reflections. Further undesired issues with external DC block capacitors include component cost, size, and reliability. In particular, large computing/networking systems which implement millions of I/Os can benefit greatly by eliminating the cost, area, and potential unreliable external DC block connections due to manufacturing errors.
To eliminate the external DC block capacitor while still enabling transmit to receive common-mode isolation, an AC coupled common mode isolation circuit can be added directly on the receiver integrated circuit. Problems which immediately arise when taking this approach include signal amplitude loss due to a capacitive divider formed by the integrated AC coupling cap with the signal amplifier parasitic input capacitance, and signal integrity loss due to potentially large “baseline wander”, or DC signal level variation, induced by variations in transmitted data as the received signal passes through the integrated AC coupling path. In particular, long runs of 1s or 0s can induce a transient bias on the differential DC component of the received signal after the integrated DC block capacitors, which can degrade the receiver sensitivity. This problem is more severe for an integrated DC block solution, since the needed isolation capacitors cannot be made as large as external DC block capacitors.
More specifically, external DC block capacitors often use capacitance values of approximately 100 nF in 50 ohm transmission systems, while an integrated capacitor, due to both die area and self-parasitic capacitance limitations, can only use a capacitance value of approximately 2 pF, which is 50,000 times smaller than the external DC block capacitor. This problem can be mitigated in an on-chip system design by using larger common mode termination resistance. As an example, a 100 k ohm common mode termination resistance, which is 2,000 times larger than the 50 ohm terminations used in the external line, might be used in conjunction with a high input impedance (MOS) active receiver input amplifier. However, this larger resistor does not make up the needed difference in AC coupling time constant to maintain needed differential baseline stability, since the time constant of 100 k and 2 pF (200 ns) is still much smaller than the time constant achievable with an external DC block capacitor (˜5 us). Therefore, a method to mitigate the baseline wander associated with a smaller integrated DC block capacitor/RC time constant must be used to enable a practical integrated DC block solution.
A known solution to the baseline wander problem for integrated AC coupling systems is referred to as the Decision-Feedback Restore (DFR) based approach. In this approach, received data is detected, and fed back into the AC coupling circuit in a way designed to compensate baseline drift arising from the AC highpass corner formed by the series integrated DC block capacitors and the bias generation resistor loads. Although this approach will compensate baseline drift, the technique requires both detection of received data, and dynamic addition of received data signals to the input network with a precise, adapted gain control through a transmission re-generation circuit. In addition, if the received transmission signal has a duty cycle error (non-equal time duration of 1 and 0 data transmissions for binary line signaling), the DFR based system may not be able to correctly compensate the baseline drift due to transient baseline wander effects induced by the transmitter duty cycle error. Finally, this approach adds unwanted power to the receiver system design, by requiring both re-generation of the received high-speed data, and summing of the received data to the input signal with associated gain control and gain adaptation methods.